APV Sequencer

The APV sequencer (fig. ) is the core of the HEPHY setup.

Figure: Block diagram of the HEPHY APV sequencer.

The module is driven by an external clock source (usually $40\,\rm MHz$). Triggers are either derived from an input on the front panel (``hardware triggers'') or generated by a VME command (``software triggers''). The hardware triggers have to pass through a D-Flip-Flop to synchronize with the clock. There, incoming triggers are only accepted if they are at logically high level during the clock edge. Synchronized triggers are then sent through a programmable veto logic which can block them. By default, the veto logic allows only a single trigger until its state is cleared by VME. However, the number of allowed trigger pulses can be set between one and eight. The veto state can also be set by a VME command to disable hardware triggers at all. Moreover, the veto logic ensures that the minimum distance between subsequent triggers is three clock cycles. Otherwise, the pattern would be interpreted as a special symbol (see tab. , p. ).

The effect of hardware triggers which have passed the veto logic or software triggers depends on the mode of operation. Either the trigger is delayed in a shift register or a programmable bit pattern is taken from an internal memory. In the first case, a digital pipeline of programmable length is used to delay the trigger sequence arriving at its input. Several triggers can be allowed to pass through the veto logic, consequently being delayed and streamed to the APV. This feature is useful to study the effect of frequent particle triggers. The second mode is mainly used for sending special symbols on the trigger line. Four different sequences of 256 bits are stored in an internal memory. One of them or several in parallel can be activated by a software or hardware trigger. By default, the four sequences are loaded with soft reset (101), calibration ($110\ldots 011$), a software and a hardware trigger ( $000\ldots 010 \ldots$) at different positions. To send an APV reset, the 101 sequence is issued by software. For internal calibration, the 11-memory together with a software trigger is activated and the calibration request is followed by another 11-pattern to dump the calibration pulse of opposite polarity (see section , p. ). The sequencer can also be used to generate a series of subsequent APV triggers initiated by a single hardware trigger. With the APV25 in multi-peak mode, this feature allows to effectively get a sequence of samples separated only by a single clock cycle. This powerful feature will be presented together with measurements in more detail in section , p. .

A trigger sequence can signal the VME-ADC to start a conversion sequence but may not necessarily do so. In fact, such a ``hold'' signal is issued except when only the soft reset or pure calibration requests are activated, since neither of these produce any APV output. The calibration pulse is only seen in conjunction with a software trigger, which also generates a hold signal for the ADC.

Voltage regulators provide the power for an attached repeater board. The clock which is sent to the repeater can be delayed to match the phase of the trigger signals and finally, a hard reset signal for the APV can be generated by a VME command. For test purposes, the trigger propagation can be switched to transparent mode, where the whole processing is bypassed and the input is directly sent to the repeater.