APVMUX

A CMS silicon strip detector module includes four or six APV25S1 chips and one APVMUX chip [51] to multiplex the output of APV pairs together onto a single line. Thus, the APVMUX core is a set of fast switches.

The APV clock is $40\,\rm MHz$, but the output is only clocked with $20\,\rm MHz$. After a 101 reset sequence, the output begins on even or odd system clock periods, depending on whether the $\rm I^2C$ address of that chip is even or odd. Thus, the output frame of odd chips is delayed by $25\,\rm ns$ with respect to even chips. This allows the APVMUX to switch between even and odd chips, presenting the stable second half of each sample. This scheme is illustrated by fig. .

Figure: APVMUX switching between two APV25 output lines.

The APVMUX includes an $\rm I^2C$ interface for choosing different termination resistors. By default, each input is terminated with $50\,\rm\Omega$ against the center voltage. Apart from the switching circuit, the APVMUX chip also includes a full implementation of the PLL-Delay described in the following section.