APSP

An analog pulse shape processor (APSP) is used to perform the deconvolution algorithm (see section , p. ). As shown in fig. , it is composed of a charge amplifier with a switched capacitor network.

Figure: Schematics of the APV25 analog pulse shape processor (APSP).

The charge of three samples is converted to a voltage and consecutively stored onto three capacitors (shown in the center between ro and ri switches). Their sizes and thus the stored charges scale with the three weights used in the deconvolution method. Finally, all charges are added and the resulting voltage is applied to the sample/hold circuit. The second capacitor is discharged in reverse polarity as the corresponding weight is negative. In peak mode, only the first capacitor is charged with the single sample, while the second capacitor is used to subtract the APSP reset level, resulting in the same pedestal voltage level in either mode. Moreover, the first capacitor is smaller in peak mode to achieve the same gain as in deconvolution mode.

Figure: Timing of the switches in the APSP in peak (left) and deconvolution (right) modes.

Fig.  shows the sequence in which the switches are operated for both peak (left) and deconvolution (right) modes. The reset frequency driving the APSP circuit is 1/70 of the system clock. Thus, the chip output signals are always synchronous to the APSP reset, regardless of the arrival time of a trigger signal.

One APSP channel consumes $0.2\,\rm mW$ of power. The overall gain of the analog chain is $100\,\rm mV/MIP$ with a nonlinearity of less than $0.6\%$ and $2\%$ over a $5\,\rm MIP$ range in peak and deconvolution modes, respectively. The noise in deconvolution mode is higher than in peak mode because the rising edge of the shaper output, which is used for the third sample, is subjected to slewing effects for large signals.