Multiplexer and Output Buffer

The sampled output of the APSP is sent to a single output line through a three-stage multiplexer. Its principle is shown in fig. . Due to the staged multiplexing, the output order of the 128 channels does not correspond to the natural channel order. The following calculation must be performed to retrieve the physical channel number $c$ from output sample number $n$:

$$c=32\left(n \bmod 4\right) + 8\;{\rm int} \left(\frac{n}{4} \right) - 31\;{\rm int} \left( \frac{n}{16} \right)$$ (4.1)

Figure: Principal structure of the APV25 multiplexer.

Fig.  shows the multiplexer circuit.

Figure: Schematics of the APV25 multiplexer.

The APSP output voltage is first converted into a current, which allows faster and more linear switching with less crosstalk. The conductance of the input stage can be selected by switching on or off several parallel resistors. This allows trimming of the multiplexer gain since the accuracy of chip internal resistors is limited to about $20\%$. Channels which are not switched through have their currents dumped into a dummy load. This is a waste of power but ensures that the voltages are not affected by the switching procedure. To the bottom right of fig. , a circuit which inserts digital signals to the output line, is shown. The digital logic levels are $\pm 400\,\rm\mu A$.

The analog gain at the output of the multiplexer is $100\,\rm\mu A/MIP$ and the power consumption of the whole multiplexer is $22\,\rm mW$ at the nominal input bias current of $50\,\rm\mu A$.

Figure: Schematics of the APV25 output buffer.

The output buffer shown in fig.  finally amplifies the multiplexer output current and splits it into differential channels. Both output lines have an analog gain of $1\,\rm mA/MIP$, resulting in a differential signal of $2\,\rm mA/MIP$ and differential logic levels of $\pm 8\,\rm mA$. The output buffer power consumption is $20\,\rm mW$.