Pipeline

The shaper output is sampled at clock intervals and stored in the analog pipeline, which is actually realized as a ring buffer of 192 cells with cycling write and read pointers. Their distance determines the latency time between particle signal and trigger arrival. With a clock frequency of $40\,\rm MHz$, the maximum time allowed for this trigger decision is more than $4\,\rm\mu s$, well covering the CMS first-level trigger delay of $3.2\,\rm\mu s$. After receiving a trigger, it takes more than $5\,\rm\mu s$ to send all pipeline data to the output line through a multiplexer. To protect valuable information from being overwritten, a FIFO with a depth of 32 locations stores the pipeline addresses of those cells waiting for readout. These marked cells are then skipped by the write pointer until the data are actually passed on. In peak mode, only a single sample is retained, which corresponds to the maximum of the CR-RC shaping curve when clock and trigger latency are properly adjusted. Three cells are marked in deconvolution mode for later processing by the APSP. This procedure avoids dead time while keeping a serial readout scheme.

Figure: Schematics of a single analog pipeline cell of the APV25.

Fig.  shows one of the $128 \times 192$ capacitor cells of the APV25. Due to a limitation in the total area of metal-insulator-metal structures allowed within the chip, nFET transistors with the size $W/L=7/7\,\rm\mu m$ are used which have a gate capacitance of $280\,\rm fF$. These gate capacitors are operated in strong inversion to ensure the best linearity. Normally, the switches on either side of the capacitor are open, only activated by write and read pointers, respectively.