DCU

The Detector Control Unit is monitoring low voltages, the detector current and temperature. Fig.  shows the its function on a silicon detector module. A small resistor is inserted in the ground connection of the polysilicon resistors to measure the voltage drop which scales with the detector leakage current. Four equal resistors between the supply rails, tapped at $\rm VDD/2$ and $\rm VSS/2$, are used to monitor the supply voltages. Moreover, an external NTC thermistor measures the silicon detector temperature, while an integrated temperature sensor monitors the DCU chip temperature.

Figure: Connections of the DCU on a silicon detector module.

Figure: Block diagram of the DCU.

The DCU architecture is shown in fig. . Seven inputs and the internal temperature sensor are multiplexed onto an ADC with 12 or optionally 14 bits resolution. The reference voltage for the ADC is generated normally from an internal bandgap diode, but can be overridden by an external source for test purposes. The ADC is implemented in a single slope serial architecture, where a linear ramp is obtained by charging or discharging a capacitor with a constant current. The analog input voltage is compared with the linear ramp and a counter, which is fed from the $40\,\rm MHz$ system clock, and stops at the trip point of a comparator. A possible offset is compensated by averaging two consecutive measurements with opposite slopes. Thus, a digitization with 14 bits resolution can be achieved with a sampling time shorter than $1\,\rm ms$. The ADC allows rail-to-rail input due to a complementary discriminator stage. The negative input range is covered by a pFET based discriminator, while an nFET type takes care of positive input. The ADC control and readout is done by the $\rm I^2C$ interface. Similar to the PLL-Delay, the digital logic is designed for triple-voting to withstand SEUs.