Digital SEUs

The SEU cross-section $\sigma$ is defined by the number of upsets $N$ divided by the fluence $\Phi$ accumulated during the measurement time,

$$\sigma=\frac{N}{\Phi}\quad.$$ (5.3)

If an electronic structure was fully sensitive to every crossing particle, the cross-section would equal the physical area of the structure. In reality, this certainly never is the case. In particular, the ionization potential of pions is by far too low to generate a single event upset. Only secondaries, such as recoil atoms produced within the sensitive layer, can achieve this condition.

More than 3000 single event upsets were observed in total during this pion irradiation with a cross-section slightly depending on the temperature. Tab.  compares the results for warm and cold operation. The SEU cross-section at the operating temperature of $-10^{\circ}\,\rm C$ will be used for further calculations. No dependence of the digital SEU rate on mode or latency settings was measured.

Table: Digital SEU cross-section of $300\,\rm MeV/c$ $\pi^+$ on the APV25S1.

Temperature $\rm [^{\circ}\,C]$	SEU cross-section $\rm [cm^2]$
+20	$1.99 \cdot 10^{-12}$
-10	$2.25 \cdot 10^{-12}$

Figure: Distribution of digital single event upsets.

Each SEU can result in one single effect or a combination of effects detected by the software checks. Fig.  shows the distribution of all observed combinations of digital single event upsets.

Each SEU can be assigned to one of three digital blocks, which are pipeline and control logic, the FIFO logic or the $\rm I^2C$ registers. The SEU cross-section of each block is compared to the actual sensitive area on the chip in fig. , revealing principal agreement. More than $96\%$ of all SEUs are pipeline related, corresponding to the largest digital block in the physical layout of the chip.

Figure: Digital SEU cross-section and sensitive area for three different logic blocks on the APV25S1.

Figure: Waiting time distribution between two digital SEUs in any of the eight APV25S1.

The statistical nature of SEUs can be shown by their waiting time distribution (fig. ). Ideally, this distribution should follow an exponential decay. However, the measurement procedure did not allow continuous SEU detection. During the digital optical transceiver tests and the measurement of voltages and currents, which took about $15\,\rm s$ together, the APVs were not read out and thus no SEUs could be detected during that period. The hole between $30$ and $45\,\rm s$ in fig.  corresponds to this dead time. SEUs produced within this period were detected immediately after finishing the other measurements, leading to the peak after the hole. The hole and peak structure repeats with a period of one minute due to the cycling measurement procedure. Apart from this artefact, the waiting time distribution demonstrates the random appearance of single event upsets.

When a single event upset occurs, the next data frame is corrupted. If the error bit is set, the same frame data are returned with future triggers until the chip receives either hard or soft reset. Bias registers which have been corrupted by a SEU may or may not affect the data. Thus, it seems advantageous to send a reset and reload the registers from time to time. All SEUs observed in this test could be cleared by a combination of hard and soft reset; no permanent effects were detected.

A similar test has been performed with heavy ions [66]. By variation of the ions and their energy, the threshold energies required to generate various types of single event upsets were measured. Fig.  compares the cross-sections obtained by heavy ions to the pion results. The $\rm I^2C$ register cross-section has been split into bit errors in either direction. The factor of approximately $10^8$ between heavy ions and pions reflects the fact that only secondary particles generated by a small fraction of pions cause a single event upset.

Figure: APV25 digital SEU cross-section comparison between heavy ions and pions.